A gate-last CMOS fabrication process is often used for material availability and stress-induced performance enhancement reasons. Also called a replacement-gate process, the gate-last approach generally requires a high temperature anneal after the gate dielectric is deposited in order to improve reliability of the dielectric.
Thus every component of the device that is present prior to the anneal must be compatible with high processing temperatures. One aspect of the device design particularly impacted by this requirement is the silicidation process commonly employed to form source and drain contacts. In this regard, with conventional device fabrication techniques, the use of a replacement gate process forces the device design to either have a high temperature compatible salicide or to employ a non self-aligned trench silicide.
While a high temperature compatible material will permit the formation of a self-aligned silicide (a salicide), desirable metals such as nickel cannot be used. Alignment issues are prevalent with a trench silicide scheme, especially when dealing with scaled device dimensions.
Thus, improved salicide techniques that are compatible with a replacement gate process would be desirable.